The disclosure relates generally to processing and fabrication techniques for semiconductor devices, and more particularly, to photolithographic mask operation activities including creation, post processing, fabrication, inspection, disposition and repair of photolithographic masks.
Semiconductor fabrication techniques often utilize a mask or reticle in a conventional lithographic system to project an image onto a semiconductor wafer, wherein radiation is provided through (or reflected off) the mask/reticle, and passed through a focusing optical system to form the image (e.g., an integrated circuit pattern). The semiconductor wafer is positioned to receive the radiation transmitted through (or reflected off) the mask/reticle such that the image formed on the wafer corresponds to the pattern on the mask/reticle. The radiation source may be light, such as ultraviolet light, vacuum ultraviolet (VUV) light, extreme ultraviolet light (EUV), deep ultraviolet light (DUV), mid ultraviolet light (MUV) or optical sources. In addition, the radiation may also be x-ray radiation, e-beam radiation, energized ions or particles, etc. Generally, the formed image is projected on the wafer in order to pattern a layer of material, such as a photoresist material. The photoresist material, in turn, may be utilized to define doping regions, deposition regions, etching regions, or other structures associated with the manufacture of integrated circuits (ICs).
Each time that a layer of material is exposed to radiation, a mask must be used to expose only the desired areas to the radiation, and to protect the other areas from exposure. The mask is created from circuit layout data. That is, the geometric elements described in layout design data define the relative locations or areas of the circuit device that will be exposed to radiation through the mask. A mask or reticle writing tool is used to create the mask based upon the layout design data, after which the mask can be used in a photolithographic process. The image created in the mask is often referred to as the intended or target mask image, while the image created on the substrate, by employing the mask in the photolithographic process, is referred to as the printed or wafer image.
As designers and manufacturers continue to increase the number of circuit components in a given area and/or shrink the size of circuit components, the shapes reproduced on the substrate become smaller and are placed closer together. This reduction in feature size increases the difficulty of faithfully reproducing the image intended by the layout design onto the substrate. In addition, the size of the features to be produced is getting smaller relative to the wavelength of the light, thus there is additional distortion from diffraction and other optical effects. One reason for non-perfect yields is that as feature sizes shrink, the dominant cause of defects change. In smaller process technologies, for example the nanometer process technology, a dominant source of yield loss is pattern-dependent effects. These defects can be the result of the design's features being smaller than the wavelength of light. As a result, the physical effects of light at these smaller feature sizes must be accounted for.
Various common techniques exist for mitigating these effects. For example, resolution enhancement technology (RET) manufacturability and resolution improvement techniques, such as scattering bars and sub-resolution assist features, double or multiple patterning, and phase shift masks (PSM), are commonly employed to prepare physical layout designs for manufacturing. RET lithographic compensations such as optical process correction (OPC) techniques for distortion correction are typically employed as well. Additionally, physical verification techniques that assist in accounting for issues such as planarization and antenna effects are also employed on physical layout designs. Although these extensive modifications to the physical layout design can result in a mask layout design unrecognizable by the designer, the resulting manufactured circuit matches the designer's intent. Application of these techniques requires the optical lithographic process to be simulated. This simulation is often accomplished by modeling the optical lithographic process. Generation of an optical model first requires that various designs be manufactured by the optical process to be modeled. Subsequently, measurements are taken of the manufactured design and models may be generated based upon the measurements of the actual manufactured design and the intended design. As indicated above, designs and the optical lithographic processes used to manufacture the designs are increasing in complexity. Accordingly, generation of optical models as well as application of resolution enhancement techniques in addition to optical proximity correction is increasingly burdensome in terms of post processing. There are also correspondingly increasing overheads in mask write times and repair requirements.
Photolithography masks are fabricated at a significant cost and time. One of the cost drivers in mask production is the need for producing minimum defect masks, through dispositioning and repair. Other costs are long lead times as well as the direct fabrication costs attributable to post processing, mask writing, and fabrication. For example, OPC is becoming increasingly non-constrained, resulting in an explosion of additional shapes and edge fragments. Changing OPC fragmentation rules increases shot counts, and correspondingly increases the e-beam mask write times for mask fabrication. In addition to the direct costs, the fabrication times for creating a new mask can delay product qualification, resulting in further economic loss.